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Bus Configuration
Low Skew Clock Buffer
CLOCK GEN.
100 MHZ
MPC8272
DLLOUT
CLKIN1
CLKIN2
IN
OUT4
OUT1
OUT2
OUT3
PCI Device
#1
PCI Device
#2
PCI Device
#3
Figure 5-4. PCI Clock Generator Scheme
5.3
Bus Configuration
The MPC8272on the board is configured in one possible bus mode, which is single
MPC8272 mode.
5.3.1
Single PowerQUICC II Mode
The MPC8272 is configured in single MPC8272 mode, assuming only one MPC8272 on
the 60x bus with no support for external master access. This configuration allows for
internal address multiplexing to occur, which makes external address multiplexers
redundant and unused, improving SDRAM performance.
5.4
Buffering
To achieve optimal performance, it is necessary to reduce the capacitive load over the 60X
bus as much as possible. The slower devices on the bus, that is, the Flash SIMM, E 2 PROM,
ATM UNI M/P interface, PCI interrupt controller and the BCSR are buffered, while the
SDRAM is not buffered from the 60X bus.
Latches are provided over address and strobe (when necessary) lines while transceivers are
provided for data. Use is done with 74ALVT buffers (by Philips) which are 3.3 V operated
and 5-V tolerant 1 , and provide bus hold to reduce pull-up/pull-down resistors count (as the
MPC8272 requires). This type of buffer reduces noise on board due to reduced transition
amplitude.
To reduce noise and reflections further, serial damping resistors are placed over SDRAM
address and all MPC8272 strobe lines.
The data transceivers are open only if there is an access to a valid 2 buffered board address
or during hard reset configuration 3 . Data conflicts are avoided in case an unbuffered
1 Required
for Flash, E 2 PROM, Interrupt Controller and BCSR
2 An
address which is covered in a Chip-Select region, that controls a buffered device.
3 To allow a configuration word stored in the Flash/E 2 PROM memory to become active.
MPC8272ADS User Guide
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